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authorDavid Li <li.davidm96@gmail.com>2015-12-20 15:02:13 -0500
committerDavid Li <li.davidm96@gmail.com>2015-12-20 15:02:13 -0500
commit24f8673dce3f8ac8658681f16d856c45dded377a (patch)
tree803c292697a6ddbd16231dfbf7b83513a5541d2f /src
parent80c073a5c4a992598ecaf36c58d2294f6aa766d0 (diff)
Set LSB of target to 0 in JALR
Diffstat (limited to 'src')
-rw-r--r--src/simulator.rs5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/simulator.rs b/src/simulator.rs
index 607a3b5..bf39c5e 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -14,6 +14,7 @@ struct RegisterFile {
#[derive(Clone)]
struct Core {
+ // TODO: directly encode PC as u32, as architecturally specified
pc: usize,
registers: RegisterFile,
running: bool,
@@ -106,15 +107,17 @@ impl Simulator {
core.running = false;
}
else {
- let target = ((pc as i32) + inst.i_imm()) as usize;
+ let target = (((pc as i32) + inst.i_imm()) & 0xFFFFFFFE) as usize;
core.registers.write_word(inst.rd(), pc + 4);
core.pc = target;
+ return;
}
},
isa::opcodes::JAL => {
let target = ((pc as i32) + inst.uj_imm()) as usize;
core.registers.write_word(inst.rd(), pc + 4);
core.pc = target;
+ return;
}
isa::opcodes::BRANCH => {