aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorDavid Li <li.davidm96@gmail.com>2016-01-15 17:21:00 -0700
committerDavid Li <li.davidm96@gmail.com>2016-01-15 17:21:00 -0700
commit05a9968d6dafb31d0e33590d80f6eb364de50d8a (patch)
treea9ae8ef56a9d64a1405e5540dcb62df2b1c72b80 /src
parent4567214f23a63b4e4964433f4034240cc4fa6a4b (diff)
Allow stalls that do not retry instruction
Diffstat (limited to 'src')
-rw-r--r--src/isa/mod.rs2
-rw-r--r--src/lib.rs2
-rw-r--r--src/memory.rs9
-rw-r--r--src/simulator.rs12
4 files changed, 18 insertions, 7 deletions
diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index 6c4bfbc..1ac585b 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -197,7 +197,7 @@ macro_rules! isa_utype {
let mut bytes = vec![];
for offset in 0..mem::size_of::<$utype>() {
- bytes.push(Byte(((self.0 >> (8 * offset)) & 0xFF) as u8));
+ bytes.push(Byte((self.0 >> (8 * offset)) as u8));
}
bytes
diff --git a/src/lib.rs b/src/lib.rs
index a2b12f0..2aee390 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -96,9 +96,11 @@ mod tests {
let stall = Err(MemoryError::CacheMiss {
stall_cycles: memory.latency(),
+ retry: true,
});
let write_stall = Err(MemoryError::CacheMiss {
stall_cycles: memory.latency(),
+ retry: true,
});
let memory_ref = Rc::new(RefCell::new(memory));
diff --git a/src/memory.rs b/src/memory.rs
index b9f070b..052ffb7 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -23,7 +23,10 @@ use isa::{self, Instruction, IsaType};
pub enum MemoryError {
InvalidAddress,
CacheMiss {
+ /// How many cycles to stall
stall_cycles: u32,
+ /// Whether the load or store should be retried
+ retry: bool,
},
}
@@ -334,7 +337,7 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> {
fetch_request.data[offset as usize] = data;
fetch_request.waiting_on += 1;
},
- Err(MemoryError::CacheMiss { stall_cycles }) => {
+ Err(MemoryError::CacheMiss { stall_cycles, .. }) => {
fetch_request.cycles_left = stall_cycles;
continue;
},
@@ -401,12 +404,14 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> {
fetch_request.error = None;
return Err(MemoryError::CacheMiss {
- stall_cycles: fetch_request.cycles_left
+ stall_cycles: fetch_request.cycles_left,
+ retry: true,
});
}
Err(MemoryError::CacheMiss {
stall_cycles: stall,
+ retry: true,
})
}
diff --git a/src/simulator.rs b/src/simulator.rs
index 63b5eec..41331ef 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -290,9 +290,11 @@ impl<'a> Core<'a> {
match result {
Ok(value) => self.registers.write_word(inst.rd(), value),
- Err(MemoryError::CacheMiss { stall_cycles }) => {
+ Err(MemoryError::CacheMiss { stall_cycles, retry }) => {
self.stall = stall_cycles - 1;
- return; // don't increment PC
+ if retry {
+ return; // don't increment PC
+ }
},
Err(MemoryError::InvalidAddress) => {
self.trap(Trap::IllegalRead {
@@ -325,9 +327,11 @@ impl<'a> Core<'a> {
match result {
Ok(()) => (),
- Err(MemoryError::CacheMiss { stall_cycles }) => {
+ Err(MemoryError::CacheMiss { stall_cycles, retry }) => {
self.stall = stall_cycles - 1;
- return; // don't increment PC
+ if retry {
+ return; // don't increment PC
+ }
},
Err(MemoryError::InvalidAddress) => {
self.trap(Trap::IllegalWrite {