diff options
author | David Li <li.davidm96@gmail.com> | 2016-01-04 13:43:41 -0700 |
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committer | David Li <li.davidm96@gmail.com> | 2016-01-04 13:43:41 -0700 |
commit | f71937d4bb74ad0ba8937da94643ddfe403ea346 (patch) | |
tree | e28b08a9a3bdf0d356f13e4cfdab9de67e98a37d /src/simulator.rs | |
parent | b9bd878207c6b784694c15675a09636d112242d7 (diff) |
Load ELF directly
Diffstat (limited to 'src/simulator.rs')
-rw-r--r-- | src/simulator.rs | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/simulator.rs b/src/simulator.rs index f92d3d2..571fafe 100644 --- a/src/simulator.rs +++ b/src/simulator.rs @@ -75,9 +75,9 @@ impl RegisterFile { impl<'a> Core<'a> { // TODO: take Rc<RefCell<>> to Memory as well? - pub fn new(cache: SharedMemory<'a>, mmu: Box<Mmu + 'a>) -> Core<'a> { + pub fn new(entry: isa::Address, cache: SharedMemory<'a>, mmu: Box<Mmu + 'a>) -> Core<'a> { Core { - pc: 0x1002c, // TODO: hardcoded: fix later + pc: entry, registers: RegisterFile::new(), stall: 0, running: true, @@ -361,10 +361,6 @@ impl<'a> Simulator<'a> { } pub fn run(&mut self) { - // hardcode _start - self.cores[0].pc = 0x1002C; - // hardcode GP - self.cores[0].registers.write_word(isa::Register::X3, 0x108D0); // hardcode SP self.cores[0].registers.write_word(isa::Register::X2, 0x7FFC); let mut total_cycles = 0; |