Load and recognize a minimal set of instructions

1 files changed, 38 insertions, 11 deletions

diff --git a/src/simulator.rs b/src/simulator.rs
index 86ddfab..8ecf6e7 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -3,7 +3,6 @@ use binary::{Binary};
 use memory::{Memory};
 
 pub struct Simulator {
-    binary: Binary,
     num_cores: usize,
     memory: Memory,
 }
@@ -17,19 +16,25 @@ struct RegisterFile {
     registers: [u32; 32],
 }
 
+impl RegisterFile {
+    fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: u32) {
+        // TODO: should be safe to use unchecked index
+        self.registers[reg.into().as_num()] = value;
+    }
+}
+
 impl Simulator {
     pub fn new(num_cores: usize, binary: Binary) -> Simulator {
+        let memory = Memory::new(0x2000, binary);
+        // TODO: initialize GP, registers (GP is in headers)
         Simulator {
-            binary: binary,
             num_cores: num_cores,
-            memory: Memory::new(0x20000),
+            memory: memory,
         }
     }
 
     pub fn run(&mut self) {
         let mut cores = vec![Core { pc: 0x10000, }; self.num_cores];
-        // TODO: set up memory, cache, devices
-        // TODO: map binary into RAM
         loop {
             for core in cores.iter_mut() {
                 self.step_core(core);
@@ -40,19 +45,41 @@ impl Simulator {
     fn step_core(&mut self, core: &mut Core) {
         if let Some(inst) = self.memory.read_instruction(core.pc) {
             match inst.opcode() {
-                isa::opcodes::Branch => {
+                isa::opcodes::BRANCH => {
                     
-                }
-                isa::opcodes::IntegerImmediate => {
-                    
-                }
+                },
+                isa::opcodes::INTEGER_IMMEDIATE => match inst.funct3() {
+                    isa::funct3::ADDI => {
+                        println!("ADDI");
+                    }
+                    _ => {
+                        panic!("Invalid integer-immediate funct3code: 0x{:x}", inst.funct3());
+                    }
+                },
+                isa::opcodes::LOAD => match inst.funct3() {
+                     isa::funct3::LW => {
+                        println!("LW");
+                    }
+                    _ => {
+                        panic!("Invalid load funct3code: 0x{:x}", inst.funct3());
+                    }
+                },
+                isa::opcodes::STORE => match inst.funct3() {
+                     isa::funct3::SW => {
+                        println!("SW");
+                    }
+                    _ => {
+                        panic!("Invalid store funct3code: 0x{:x}", inst.funct3());
+                    }
+                },
                 _ => {
-                    
+                    panic!("Invalid opcode: 0x{:02X}", inst.opcode());
                 }
             }
         }
         else {
             // trap
         }
+        core.pc += 4;
     }
 }