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authorDavid Li <li.davidm96@gmail.com>2015-12-25 10:57:04 -0700
committerDavid Li <li.davidm96@gmail.com>2015-12-25 10:57:04 -0700
commitf235d8e500e9fd9945d07ed347ccab5214d26eba (patch)
tree24d6d9748edd2a61e38d9089450f8cbe096c751b /src/simulator.rs
parent39ce6b062b6d36495098e39dfd813212757ac4f3 (diff)
Add trait for memory interface
Diffstat (limited to 'src/simulator.rs')
-rw-r--r--src/simulator.rs48
1 files changed, 30 insertions, 18 deletions
diff --git a/src/simulator.rs b/src/simulator.rs
index bc4443c..5eb68e2 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -1,6 +1,6 @@
use isa;
use binary::{Binary};
-use memory::{Memory};
+use memory::{MemoryInterface, Memory, MemoryError};
pub struct Simulator {
num_cores: usize,
@@ -272,21 +272,22 @@ impl Simulator {
}
},
isa::opcodes::LOAD => match inst.funct3() {
- isa::funct3::LW => {
- let imm = inst.i_imm();
- let base = core.registers.read_word(inst.rs1());
- let address = ((base as isa::SignedWord) + imm) as isa::Address;
- if let Some(value) = self.memory.read_word(address) {
- core.registers.write_word(inst.rd(), value);
- }
- else {
- self.trap(core, Trap::IllegalRead {
- address: pc,
- instruction: inst,
- memory_address: address,
- });
- }
- }
+ isa::funct3::LW => {
+ let imm = inst.i_imm();
+ let base = core.registers.read_word(inst.rs1());
+ let address = ((base as isa::SignedWord) + imm) as isa::Address;
+ match self.memory.read_word(address) {
+ Ok(value) => core.registers.write_word(inst.rd(), value),
+ Err(MemoryError::CacheMiss) => return,
+ Err(MemoryError::InvalidAddress) => {
+ self.trap(core, Trap::IllegalRead {
+ address: pc,
+ instruction: inst,
+ memory_address: address,
+ });
+ }
+ }
+ },
_ => {
panic!("Invalid load funct3code: 0x{:x}", inst.funct3());
}
@@ -297,7 +298,18 @@ impl Simulator {
let base = core.registers.read_word(inst.rs1());
let val = core.registers.read_word(inst.rs2());
let address = ((base as isa::SignedWord) + imm) as isa::Address;
- self.memory.write_word(address, val);
+ match self.memory.write_word(address, val) {
+ Ok(()) => (),
+ Err(MemoryError::CacheMiss) => return,
+ Err(MemoryError::InvalidAddress) => {
+ self.trap(core, Trap::IllegalWrite {
+ address: pc,
+ instruction: inst,
+ memory_address: address,
+ memory_value: val,
+ })
+ }
+ }
}
_ => {
panic!("Invalid store funct3code: 0x{:x}", inst.funct3());
@@ -311,7 +323,7 @@ impl Simulator {
println!("Argument {:X}: {:?}", address, self.memory.read_word(address));
}
_ => {
-
+
}
},
_ => {