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authorDavid Li <li.davidm96@gmail.com>2016-01-01 11:01:38 -0700
committerDavid Li <li.davidm96@gmail.com>2016-01-01 11:01:38 -0700
commitd916938c7cd8954fa7f6d21815dc11f8aca211f9 (patch)
treef1c4dfae2c86096c7ea3d0e27a9b30493ea5c577 /src/simulator.rs
parent0440fb92abc0ac72d03787aa24238deb22abbb7b (diff)
Test use of cache in simulation
Diffstat (limited to 'src/simulator.rs')
-rw-r--r--src/simulator.rs25
1 files changed, 23 insertions, 2 deletions
diff --git a/src/simulator.rs b/src/simulator.rs
index 2238421..e882c9a 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -27,6 +27,7 @@ struct RegisterFile {
pub struct Core<'a> {
pc: isa::Address,
registers: RegisterFile,
+ stall: u32,
running: bool,
// TODO: change to memory::SharedMemory
cache: Rc<RefCell<Box<MemoryInterface + 'a>>>,
@@ -81,6 +82,7 @@ impl<'a> Core<'a> {
Core {
pc: 0x1002c, // TODO: hardcoded: fix later
registers: RegisterFile::new(),
+ stall: 0,
running: true,
cache: cache,
}
@@ -88,6 +90,12 @@ impl<'a> Core<'a> {
fn step(&mut self, inst: isa::Instruction) {
let pc = self.pc;
+
+ if self.stall > 0 {
+ self.stall -= 1;
+ return;
+ }
+
match inst.opcode() {
isa::opcodes::JALR => {
// TODO: assert funct3 is 0
@@ -273,7 +281,10 @@ impl<'a> Core<'a> {
match result {
Ok(value) =>
self.registers.write_word(inst.rd(), value),
- Err(MemoryError::CacheMiss {..}) => return,
+ Err(MemoryError::CacheMiss { stall_cycles }) => {
+ self.stall = stall_cycles;
+ return;
+ },
Err(MemoryError::InvalidAddress) => {
self.trap(Trap::IllegalRead {
address: pc,
@@ -296,7 +307,10 @@ impl<'a> Core<'a> {
let result = self.cache.borrow_mut().write_word(address, val);
match result {
Ok(()) => (),
- Err(MemoryError::CacheMiss {..}) => return,
+ Err(MemoryError::CacheMiss { stall_cycles }) => {
+ self.stall = stall_cycles;
+ return;
+ },
Err(MemoryError::InvalidAddress) => {
self.trap(Trap::IllegalWrite {
address: pc,
@@ -350,12 +364,16 @@ impl<'a> Simulator<'a> {
self.cores[0].registers.write_word(isa::Register::X3, 0x108D0);
// hardcode SP
self.cores[0].registers.write_word(isa::Register::X2, 0x7FFC);
+ let mut total_cycles = 0;
+ let mut stall_cycles = 0;
loop {
let mut ran = false;
+ total_cycles += 1;
for core in self.cores.iter_mut() {
if !core.running {
continue;
}
+ if core.stall > 0 { stall_cycles += 1; }
let inst = self.memory.borrow_mut().read_instruction(core.pc);
if let Some(inst) = inst {
core.step(inst);
@@ -363,10 +381,13 @@ impl<'a> Simulator<'a> {
else {
// TODO: trap
}
+
+ core.cache.borrow_mut().step();
ran = true;
}
if !ran {
println!("All cores are not running, stopping...");
+ println!("Stalled cycles: {} of {}", stall_cycles, total_cycles);
break;
}
}