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authorDavid Li <li.davidm96@gmail.com>2015-12-16 16:15:29 -0500
committerDavid Li <li.davidm96@gmail.com>2015-12-16 16:15:29 -0500
commit55a9ca94d64249280438da9b90186e0a4973f90d (patch)
tree7c2f4d5abdce0b0b00e75bfaa49e154b9be52868 /src/simulator.rs
parent98475b71bcf5a89c8c1c4c59a0c9f9ade74494f5 (diff)
Load and recognize a minimal set of instructions
Diffstat (limited to 'src/simulator.rs')
-rw-r--r--src/simulator.rs49
1 files changed, 38 insertions, 11 deletions
diff --git a/src/simulator.rs b/src/simulator.rs
index 86ddfab..8ecf6e7 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -3,7 +3,6 @@ use binary::{Binary};
use memory::{Memory};
pub struct Simulator {
- binary: Binary,
num_cores: usize,
memory: Memory,
}
@@ -17,19 +16,25 @@ struct RegisterFile {
registers: [u32; 32],
}
+impl RegisterFile {
+ fn write_word<T: Into<isa::Register>>(&mut self, reg: T, value: u32) {
+ // TODO: should be safe to use unchecked index
+ self.registers[reg.into().as_num()] = value;
+ }
+}
+
impl Simulator {
pub fn new(num_cores: usize, binary: Binary) -> Simulator {
+ let memory = Memory::new(0x2000, binary);
+ // TODO: initialize GP, registers (GP is in headers)
Simulator {
- binary: binary,
num_cores: num_cores,
- memory: Memory::new(0x20000),
+ memory: memory,
}
}
pub fn run(&mut self) {
let mut cores = vec![Core { pc: 0x10000, }; self.num_cores];
- // TODO: set up memory, cache, devices
- // TODO: map binary into RAM
loop {
for core in cores.iter_mut() {
self.step_core(core);
@@ -40,19 +45,41 @@ impl Simulator {
fn step_core(&mut self, core: &mut Core) {
if let Some(inst) = self.memory.read_instruction(core.pc) {
match inst.opcode() {
- isa::opcodes::Branch => {
+ isa::opcodes::BRANCH => {
- }
- isa::opcodes::IntegerImmediate => {
-
- }
+ },
+ isa::opcodes::INTEGER_IMMEDIATE => match inst.funct3() {
+ isa::funct3::ADDI => {
+ println!("ADDI");
+ }
+ _ => {
+ panic!("Invalid integer-immediate funct3code: 0x{:x}", inst.funct3());
+ }
+ },
+ isa::opcodes::LOAD => match inst.funct3() {
+ isa::funct3::LW => {
+ println!("LW");
+ }
+ _ => {
+ panic!("Invalid load funct3code: 0x{:x}", inst.funct3());
+ }
+ },
+ isa::opcodes::STORE => match inst.funct3() {
+ isa::funct3::SW => {
+ println!("SW");
+ }
+ _ => {
+ panic!("Invalid store funct3code: 0x{:x}", inst.funct3());
+ }
+ },
_ => {
-
+ panic!("Invalid opcode: 0x{:02X}", inst.opcode());
}
}
}
else {
// trap
}
+ core.pc += 4;
}
}