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authorDavid Li <li.davidm96@gmail.com>2015-12-16 16:15:29 -0500
committerDavid Li <li.davidm96@gmail.com>2015-12-16 16:15:29 -0500
commit55a9ca94d64249280438da9b90186e0a4973f90d (patch)
tree7c2f4d5abdce0b0b00e75bfaa49e154b9be52868 /src/memory.rs
parent98475b71bcf5a89c8c1c4c59a0c9f9ade74494f5 (diff)
Load and recognize a minimal set of instructions
Diffstat (limited to 'src/memory.rs')
-rw-r--r--src/memory.rs15
1 files changed, 11 insertions, 4 deletions
diff --git a/src/memory.rs b/src/memory.rs
index 854b0ea..3409ed4 100644
--- a/src/memory.rs
+++ b/src/memory.rs
@@ -1,21 +1,28 @@
use isa::{Instruction};
+use binary::{Binary};
pub struct Memory {
memory: Vec<u32>,
}
impl Memory {
- pub fn new(size: usize) -> Memory {
+ pub fn new(size: usize, binary: Binary) -> Memory {
+ let mut memory = binary.words.clone();
+ if size > memory.len() {
+ let remainder = size - memory.len();
+ memory.reserve(remainder);
+ }
Memory {
- memory: Vec::with_capacity(size),
+ memory: memory,
}
}
pub fn read_word(&self, address: usize) -> Option<u32> {
- self.memory.get(address).map(Clone::clone)
+ // memory is word-addressed but addresses are byte-addressed
+ self.memory.get(address / 4).map(Clone::clone)
}
pub fn read_instruction(&self, pc: usize) -> Option<Instruction> {
- self.memory.get(pc).map(Clone::clone).map(Instruction::new)
+ self.memory.get(pc / 4).map(Clone::clone).map(Instruction::new)
}
}