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authorDavid Li <li.davidm96@gmail.com>2015-12-16 16:15:29 -0500
committerDavid Li <li.davidm96@gmail.com>2015-12-16 16:15:29 -0500
commit55a9ca94d64249280438da9b90186e0a4973f90d (patch)
tree7c2f4d5abdce0b0b00e75bfaa49e154b9be52868 /src/isa/mod.rs
parent98475b71bcf5a89c8c1c4c59a0c9f9ade74494f5 (diff)
Load and recognize a minimal set of instructions
Diffstat (limited to 'src/isa/mod.rs')
-rw-r--r--src/isa/mod.rs13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index 5e9a7dc..ac8ce45 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -1,6 +1,7 @@
pub mod opcodes;
+pub mod funct3;
-enum Register {
+pub enum Register {
X0 = 0,
X1 = 1,
X2 = 2,
@@ -15,6 +16,12 @@ enum Register {
X11 = 11,
}
+impl Register {
+ pub fn as_num(self) -> usize {
+ self as usize
+ }
+}
+
pub struct Instruction {
word: u32,
}
@@ -29,4 +36,8 @@ impl Instruction {
pub fn opcode(&self) -> u32 {
self.word & 0x7F
}
+
+ pub fn funct3(&self) -> u32 {
+ (self.word >> 12) & 0x3
+ }
}