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author | David Li <li.davidm96@gmail.com> | 2016-01-03 12:58:45 -0700 |
---|---|---|
committer | David Li <li.davidm96@gmail.com> | 2016-01-03 12:58:45 -0700 |
commit | b67738961840a9904547322ec0816115ad3215e1 (patch) | |
tree | 9645a6290b55443795c82be8d197a9bf00391d7e | |
parent | 7ffec2b2ffe4246a6fe63f5b59ca399ae236236f (diff) |
Write value to cache as well
-rw-r--r-- | src/memory.rs | 78 |
1 files changed, 43 insertions, 35 deletions
diff --git a/src/memory.rs b/src/memory.rs index 9b4ab0a..9f14700 100644 --- a/src/memory.rs +++ b/src/memory.rs @@ -55,9 +55,9 @@ pub trait MemoryInterface { match result { Ok(word) => match offset { 0 => Ok((word & 0xFF) as isa::Byte), - 1 => Ok((word & 0xFF00) as isa::Byte), - 2 => Ok((word & 0xFF0000) as isa::Byte), - 3 => Ok((word & 0xFF000000) as isa::Byte), + 1 => Ok(((word & 0xFF00) >> 8) as isa::Byte), + 2 => Ok(((word & 0xFF0000) >> 16) as isa::Byte), + 3 => Ok(((word & 0xFF000000) >> 24) as isa::Byte), _ => panic!(""), }, Err(e) => Err(e), @@ -233,38 +233,35 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> { if let Some(ref mut fetch_request) = set.fetch_request { if fetch_request.cycles_left > 0 { fetch_request.cycles_left -= 1; - continue; } - else { - // read all the words in a line from the next - // level, until we get a stall - - for offset in fetch_request.waiting_on..self.block_words { - let result = self.next_level - .borrow_mut() - .read_word(fetch_request.address + (4 * offset)); - match result { - Ok(data) => { - fetch_request.data[offset as usize] = data; - fetch_request.waiting_on += 1; - }, - Err(MemoryError::CacheMiss { stall_cycles }) => { - fetch_request.cycles_left = stall_cycles; - continue; - }, - Err(MemoryError::InvalidAddress) => { - fetch_request.error = - Some(MemoryError::InvalidAddress); - continue; - } + // read all the words in a line from the next + // level, until we get a stall + + for offset in fetch_request.waiting_on..self.block_words { + let result = self.next_level + .borrow_mut() + .read_word(fetch_request.address + (4 * offset)); + match result { + Ok(data) => { + fetch_request.data[offset as usize] = data; + fetch_request.waiting_on += 1; + }, + Err(MemoryError::CacheMiss { stall_cycles }) => { + fetch_request.cycles_left = stall_cycles; + continue; + }, + Err(MemoryError::InvalidAddress) => { + fetch_request.error = + Some(MemoryError::InvalidAddress); + continue; } } - - // All words fetched, write to cache - set.tag = fetch_request.tag; - set.contents = fetch_request.data.clone(); - set.valid = true; } + + // All words fetched, write to cache + set.tag = fetch_request.tag; + set.contents = fetch_request.data.clone(); + set.valid = true; } set.fetch_request = None; @@ -323,10 +320,21 @@ impl<'a> MemoryInterface for DirectMappedCache<'a> { // Write-allocate policy match self.read_word(address) { Ok(_) => { - // Write-through policy - match self.next_level.borrow_mut().write_word(address, value) { - Ok(()) => Ok(()), - Err(e) => Err(e), + let (tag, index, offset) = self.parse_address(address); + let ref mut set = self.cache[index as usize]; + + if set.valid && set.tag == tag { + set.contents[(offset / 4) as usize] = value; + // Write-through policy + let result = self.next_level.borrow_mut() + .write_word(address, value); + match result { + Ok(()) => Ok(()), + Err(e) => Err(e), + } + } + else { + panic!("Could not find supposedly read word"); } }, Err(e) => Err(e), |