Fix compile errors

2 files changed, 16 insertions, 8 deletions

diff --git a/src/isa/mod.rs b/src/isa/mod.rs
index c8aa290..565e6e0 100644
--- a/src/isa/mod.rs
+++ b/src/isa/mod.rs
@@ -128,17 +128,25 @@ impl Instruction {
 
     pub fn s_imm(&self) -> i32 {
         let low = (self.word >> 7) & 0x1F;
-        let high = ((self.word as i32) >> 25) & 0x7F;
-        (high << 7) | low
+        let high = (((self.word as i32) >> 25) & 0x7F) as u32;
+        ((high << 7) | low) as i32
     }
 
     pub fn uj_imm(&self) -> i32 {
         // Want zero-extension
         let low1 = (self.word >> 21) & 0x3FF;
-        let low11 = (self.word >> 19) & 0x1;
+        let low11 = (self.word >> 20) & 0x1;
         let low12 = (self.word >> 12) & 0xFF;
         // Want sign-extension
-        let low20 = ((self.word as i32) >> 30) & 0x1;
-        (low20 << 20) | (low12 << 12) | (low11 << 11) | (low1 << 1)
+        let low20 = (((self.word as i32) >> 30) & 0x1) as u32;
+        ((low20 << 20) | (low12 << 12) | (low11 << 11) | (low1 << 1)) as i32
+    }
+
+    pub fn sb_imm(&self) -> i32 {
+        let low1 = (self.word >> 8) & 0xF;
+        let low5 = (self.word >> 25) & 0x3F;
+        let low11 = (self.word >> 7) & 0x1;
+        let low12 = (((self.word as i32) >> 31) & 0x1) as u32;
+        ((low12 << 12) | (low11 << 11) | (low5 << 5) | (low1 << 1)) as i32
     }
 }
diff --git a/src/simulator.rs b/src/simulator.rs
index 3ca11d9..7e7051c 100644
--- a/src/simulator.rs
+++ b/src/simulator.rs
@@ -107,15 +107,15 @@ impl Simulator {
                         core.running = false;
                     }
                     else {
-                        let target = (((pc as i32) + inst.i_imm()) & 0xFFFFFFFE) as usize;
-                        core.registers.write_word(inst.rd(), pc + 4);
+                        let target = (((pc as i32) + inst.i_imm()) as usize) & 0xFFFFFFFE;
+                        core.registers.write_word(inst.rd(), (pc + 4) as u32);
                         core.pc = target;
                         return;
                     }
                 },
                 isa::opcodes::JAL => {
                     let target = ((pc as i32) + inst.uj_imm()) as usize;
-                    core.registers.write_word(inst.rd(), pc + 4);
+                    core.registers.write_word(inst.rd(), (pc + 4) as u32);
                     core.pc = target;
                     return;
                 }