**CacheRacer TODOs** This is what remains to be done in reimplementing CacheRacer. Please email [li.davidm96@gmail.com](mailto:li.davidm96@gmail.com) with suggestions or questions. You can follow along with development at https://git.lidavidm.me/cacheracer/. ## Overall - [ ] Come up with a theme - [ ] Overall theme - [ ] Sneak attack/retreat = - [ ] White walker/dragon glass = - [ ] Arrow barrage = ## Memory - [x] Make sure `ReverseMmu` maps addresses correctly (i.e. 0x0 should map to an actual array element) - [ ] `ReverseMmu` needs to mark VA 0x0 as invalid somehow - [x] Sneak attack/retreat needs to be per-core - [x] ~~Invalidate~~/update other caches when a write is made - [ ] Implement global data structures - [ ] Player status - [ ] Core status - [ ] Cache info - [ ] Enemy memory should be inaccessible unless in sneak-attack mode ## Scoring - [x] Stop game once score reached - [ ] Provide visualization (possibly using console?) like one used at tournament ## Sneak Attack/Retreat - [ ] Test sneak attack/retreat system calls - [ ] Implement taunt array - [ ] Write array to main memory - [ ] Update or invalidate relevant cache lines ## Traps - [ ] Implement traps - [x] Write traps ("White Walkers" in Fall 2015) - [ ] Area traps ("Arrow Barrages" in Fall 2015) - [ ] Rebalance traps - [ ] Anti-write traps ("Dragon Glass" in Fall 2015) ## Development/Debugging - [ ] Write the header file - [x] Write some sample bots - [x] Publish them - [ ] Package RISC-V toolchain - [ ] Find way to shrink toolchain - [ ] Implement debugger - [ ] Debug logging - [ ] Cache misses/stalls - [ ] Traps ## Misc - [ ] Allow custom trap handling in simulator, so we can restart cores if they crash