From 3b24e7334e0da860c69307918cbfa5ea50bf4e16 Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Mon, 11 Jan 2016 09:32:29 -0700
Subject: Add printi syscall

---
 src/system.rs | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/system.rs b/src/system.rs
index 8875f28..4e48303 100644
--- a/src/system.rs
+++ b/src/system.rs
@@ -27,7 +27,7 @@ impl<'a> SyscallHandler<'a> {
 }
 
 impl<'a> SyscallHandler<'a> {
-    fn print(&mut self, core_id: usize,
+    fn prints(&mut self, core_id: usize,
              registers: &mut RegisterFile) -> Option<Trap> {
         let mut base = registers.read_word(isa::Register::X11);
         let mut string = vec![];
@@ -55,6 +55,13 @@ impl<'a> SyscallHandler<'a> {
         None
     }
 
+    fn printi(&mut self, core_id: usize,
+              registers: &mut RegisterFile) -> Option<Trap> {
+        println!("{}", registers.read_word(isa::Register::X11));
+
+        None
+    }
+
     fn enable_secondary(&mut self, core_id: usize,
                         registers: &mut RegisterFile) -> Option<Trap> {
         debug!("[syscall] [memory] Secondary cache enabled for core {}",
@@ -79,9 +86,10 @@ impl<'a> syscall::SyscallHandler for SyscallHandler<'a> {
         let syscall_number = registers.read_word(isa::Register::X10);
 
         match syscall_number {
-            22 => self.print(core_id, registers),
-            23 => self.enable_secondary(core_id, registers),
-            24 => self.disable_secondary(core_id, registers),
+            22 => self.prints(core_id, registers),
+            23 => self.printi(core_id, registers),
+            24 => self.enable_secondary(core_id, registers),
+            25 => self.disable_secondary(core_id, registers),
 
             _ => {
                 // TODO: some sort of error reporting
-- 
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