From 4ab7f50c2c144f3dbe73e051d794b84a1548c03a Mon Sep 17 00:00:00 2001
From: David Li <li.davidm96@gmail.com>
Date: Mon, 25 Jan 2016 16:42:32 -0500
Subject: feat(memory): disallow access to high memory by default

---
 src/shareable_cache.rs | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

(limited to 'src/shareable_cache.rs')

diff --git a/src/shareable_cache.rs b/src/shareable_cache.rs
index 6cc22df..a4931fc 100644
--- a/src/shareable_cache.rs
+++ b/src/shareable_cache.rs
@@ -10,12 +10,19 @@ pub const AREA_TRAP_VALUE: isa::Byte = isa::Byte(0xE4);
 pub const WRITE_TRAP_STALL: u32 = 1_000_000;
 pub const WRITE_TRAP_SET_STALL: u32 = 100;
 
+pub enum AccessibleRegion {
+    Low,
+    High,
+}
+
 /// A cache that can be used as two separate caches or one
-/// set-associative cache.
+/// set-associative cache. Disallows access to part of memory.
 pub struct ShareableCache<'a> {
     core_id: usize,
     primary: SharedCache<'a>,
     secondary: SharedCache<'a>,
+    midpoint: isa::Address,
+    home_region: AccessibleRegion,
     secondary_enabled: bool,
     use_secondary: bool,
     traps_hit: HashSet<isa::Address>,
@@ -181,13 +188,15 @@ macro_rules! write_value {
 }
 
 impl<'a> ShareableCache<'a> {
-    pub fn new(core_id: usize,
+    pub fn new(core_id: usize, midpoint: isa::Address, home: AccessibleRegion,
                cache1: SharedCache<'a>, cache2: SharedCache<'a>)
                -> ShareableCache<'a> {
         ShareableCache {
             core_id: core_id,
             primary: cache1.clone(),
             secondary: cache2.clone(),
+            home_region: home,
+            midpoint: midpoint,
             secondary_enabled: false,
             use_secondary: false,
             traps_hit: HashSet::new(),
@@ -239,6 +248,12 @@ impl<'a> MemoryInterface for ShareableCache<'a> {
         // TODO: disallow access to high or low memory unless
         // secondary cache is enabled. Remember: addresses are already
         // translated
+        if match self.home_region {
+            AccessibleRegion::Low => address >= self.midpoint,
+            AccessibleRegion::High => address < self.midpoint,
+        } && !self.secondary_enabled {
+            return Err(MemoryError::InvalidAddress);
+        }
 
         // TODO: is CacheRacer physically or virtually addressed?
         if self.secondary_enabled {
-- 
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