From 70ef4cc988e7daa240d331082e566add286089ab Mon Sep 17 00:00:00 2001 From: David Li Date: Sun, 10 Jan 2016 10:13:40 -0700 Subject: Give individual cores secondary cache access --- src/main.rs | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'src/main.rs') diff --git a/src/main.rs b/src/main.rs index c7ee66f..2f607a6 100644 --- a/src/main.rs +++ b/src/main.rs @@ -87,17 +87,25 @@ fn main() { let cache2_ref = Rc::new(RefCell::new(cache2)); let (cache1, cache2) = ShareableCache::new(cache_ref.clone(), cache2_ref.clone()); + let mut core_caches = vec![]; let mut cores = vec![]; for i in 0..4 { + let c1 = Rc::new(RefCell::new(cache1.clone())); + core_caches.push(c1.clone()); let mut core = simulator::Core::new( - i, start1, (0x100000 * (i + 1)) as u32, cache1.clone(), + i, start1, (0x100000 * (i + 1)) as u32, c1, Box::new(memory::IdentityMmu::new()) ); core.registers().write_word(isa::Register::X10, i as isa::Word); cores.push(core); + } + + for i in 4..8 { + let c2 = Rc::new(RefCell::new(cache2.clone())); + core_caches.push(c2.clone()); let mut core = simulator::Core::new( - i, start2, (0x100000 * (i + 1)) as u32, cache2.clone(), + i, start2, (0x100000 * (i + 1)) as u32, c2, Box::new(memory::ReverseMmu::new(0x4000000)) ); core.registers().write_word(isa::Register::X10, i as isa::Word); @@ -105,7 +113,6 @@ fn main() { } let steppable_caches = vec![cache_ref.clone() as memory::SharedMemory, cache2_ref]; - let core_caches = vec![cache1, cache2]; let system = SyscallHandler::new(memory_ref.clone(), core_caches); let mut simulator = simulator::Simulator::new( cores, memory_ref.clone(), steppable_caches, system); -- cgit v1.2.3