diff options
| -rw-r--r-- | src/main.rs | 12 | ||||
| -rw-r--r-- | src/shareable_cache.rs | 19 |
2 files changed, 26 insertions, 5 deletions
diff --git a/src/main.rs b/src/main.rs index a9af93e..38ab791 100644 --- a/src/main.rs +++ b/src/main.rs @@ -27,7 +27,7 @@ use rustv::memory; use rustv::simulator; use memory_tracker::MemoryTracker; -use shareable_cache::ShareableCache; +use shareable_cache::{AccessibleRegion, ShareableCache}; use system::SyscallHandler; const USAGE: &'static str = " @@ -118,9 +118,13 @@ fn main() { let mut cores = vec![]; let mut core_caches = vec![]; + let midpoint = isa::Word(0x4000000 / 2); + for i in 0..4 { let core_cache = Rc::new(RefCell::new( - ShareableCache::new(i, cache_ref.clone(), cache2_ref.clone()))); + ShareableCache::new( + i, midpoint, AccessibleRegion::Low, + cache_ref.clone(), cache2_ref.clone()))); core_caches.push(core_cache.clone()); let mut core = simulator::Core::new( i, start1, isa::Word(0x100000 * (i + 1) as u32), core_cache, @@ -133,7 +137,9 @@ fn main() { for i in 4..8 { let core_cache = Rc::new(RefCell::new( - ShareableCache::new(i, cache2_ref.clone(), cache_ref.clone()))); + ShareableCache::new( + i, midpoint, AccessibleRegion::High, + cache2_ref.clone(), cache_ref.clone()))); core_caches.push(core_cache.clone()); let mut core = simulator::Core::new( i, start2, isa::Word(0x100000 * (i + 1) as u32), core_cache, diff --git a/src/shareable_cache.rs b/src/shareable_cache.rs index 6cc22df..a4931fc 100644 --- a/src/shareable_cache.rs +++ b/src/shareable_cache.rs @@ -10,12 +10,19 @@ pub const AREA_TRAP_VALUE: isa::Byte = isa::Byte(0xE4); pub const WRITE_TRAP_STALL: u32 = 1_000_000; pub const WRITE_TRAP_SET_STALL: u32 = 100; +pub enum AccessibleRegion { + Low, + High, +} + /// A cache that can be used as two separate caches or one -/// set-associative cache. +/// set-associative cache. Disallows access to part of memory. pub struct ShareableCache<'a> { core_id: usize, primary: SharedCache<'a>, secondary: SharedCache<'a>, + midpoint: isa::Address, + home_region: AccessibleRegion, secondary_enabled: bool, use_secondary: bool, traps_hit: HashSet<isa::Address>, @@ -181,13 +188,15 @@ macro_rules! write_value { } impl<'a> ShareableCache<'a> { - pub fn new(core_id: usize, + pub fn new(core_id: usize, midpoint: isa::Address, home: AccessibleRegion, cache1: SharedCache<'a>, cache2: SharedCache<'a>) -> ShareableCache<'a> { ShareableCache { core_id: core_id, primary: cache1.clone(), secondary: cache2.clone(), + home_region: home, + midpoint: midpoint, secondary_enabled: false, use_secondary: false, traps_hit: HashSet::new(), @@ -239,6 +248,12 @@ impl<'a> MemoryInterface for ShareableCache<'a> { // TODO: disallow access to high or low memory unless // secondary cache is enabled. Remember: addresses are already // translated + if match self.home_region { + AccessibleRegion::Low => address >= self.midpoint, + AccessibleRegion::High => address < self.midpoint, + } && !self.secondary_enabled { + return Err(MemoryError::InvalidAddress); + } // TODO: is CacheRacer physically or virtually addressed? if self.secondary_enabled { |